The present invention relates to semiconductor devices and, more particularly, to high speed circuits for receiving logic signals of multiple logic families.
Many electronic systems are implemented using integrated circuits of different logic families. For example, computer systems often use complementary metal-oxide-semiconductor (CMOS) circuits to perform computational functions, low voltage differential signaling (LVDS) circuits for disk drive data signals, and positive emitter-coupled logic (PECL) circuits for clock drivers. These logic circuits are typically incompatible with each other in the sense that voltage levels specified for circuits of one logic family do not fall within the voltage range specified for circuits of a different logic family. Hence, data is lost or noise immunity is substantially impaired. For this reason, a receiver-translator circuit often is used to translate between signals of different logic families.
Most previous receivers are configured to receive signals of only one logic family, so systems must utilize a different translator for each combination of distinct logic families. The result is a higher system cost because of the need to inventory multiple translators and, since fewer translators of each type are used, the lack of economies of scale.
Other previous translators receive signals from multiple logic families. While these devices operate at a high speed for signals from at least one logic family, their specified common mode input voltage range is limited, which results in a significant speed reduction for signals whose common mode levels fall outside the specified range.
Hence, there is a need for a receiver-translator circuit that can receive signals operating over a wider common mode range while maintaining a high speed operation regardless of the common mode levels of the incoming logic signals.